It is demanded that various electronic apparatus (for example, an LSI, an MCM, a PCB and so forth) developed at present have augmented performances, higher operation speeds, reduced sizes and increased densities, and now, also functions of such apparatus have been much complicated.
For example, for higher speed operations, it is demanded that the system clock (transmission clock cycle) be approximately 300 MHz, and also it is demanded that also the signal edge speed (rising/falling speed of a signal) be set to several hundreds ps (picoseconds) as a result of the rise of the speed of the clock. Meanwhile, in order to raise the density of the mounting state, an SOP (Small Outline Package) of the surface mounting type is adopted as a package technique for an LSI from a DIP (Dual In-line Package) of the through-hole mounting type. Further, a BGA (Ball Grid Array) is adopted in recent years.
In such a situation as just described, the problem of a wiring line delay is actualized as a result of the increase in speed. Therefore, attention must be paid to a wiring line delay when an electronic circuit of an LSI, MCM, PCB or the like is designed.
An LSI of the CMOS type which is adopted frequently in common electronic apparatus has a characteristic that the power consumption is low. However, the LSI of the CMOS type has a problem in that, because operating current which flows through an element is fluctuated by a great amount by switching of gates, power supply noise is generated and another problem in that the noise margin is decreased by a drop of the amplitude voltage.
Further, as such increase in speed and reduction in size/increase in density of an apparatus as described above proceed, crosstalk noise and reflection noise caused by impedance mismatching or by a large capacitive load are generated compositely, not only a delay problem by noise occurs, but also a malfunction may possibly occur in the circuit.
A certain wiring line is subject to electric interference by a switching operation of a signal which propagates in an adjacent wiring line, and noise, which is caused by the electric interference and is superposed on a signal propagating on the wiring line, is called crosstalk noise. Such crosstalk noise exhibits an increase to a level which cannot be ignored as a reduction of the distance between wirings and increase of the signal edge speed.
In a bus line, a plurality of signal lines are wired densely, and also when signals which propagate in the signal lines are switched simultaneously, high noise is generated. This noise is called simultaneous switching noise.
Since generation of such various kinds of noise (reflection noise, crosstalk noise, simultaneous switching noise and power supply/ground bounce) as described above deteriorate the quality (signal integrity) of the waveform of a signal propagating in a circuit very much, the problem of a delay or a malfunction in signal propagation has been actualized. Further, since superposition of various kinds of noises described above on a propagation signal makes a factor of an increase of electromagnetic induction noise (radio wave radiation noise) to the outside in addition to an increase of the operating speed, also it is demanded to pay attention to EMI (electromagnetic interference) to design a circuit so that the degree to which various kinds of noise generated in the circuit have an influence on a propagation signal may be suppressed as far as possible.
To this end, it is a conventional practice to set wiring rules on the document base and urge a designer to observe the wiring rules or to provide a wiring rule check tool on the mathematical expression base as a CAD tool to automatically check whether or not the wiring rules are observed when a circuit is designed.
In wiring rules on the document base, rules on wiring line designing which can suppress generation of the various kinds of noise described above are described in advance in the form of a document, and a circuit designer refers to the document to design a circuit observing the rules. For example, parallel wiring line spaces/parallel wiring line lengths with which generation of crosstalk noise can be suppressed, wiring line lengths/branch lengths with which an influence of reflection noise can be suppressed, and so forth are set as rules.
In a wiring rule check tool on the mathematical expression base, wiring rules on the document base described above are described not in the form of a document but in the form of mathematical expressions in advance, and various dimensions regarding wiring lines obtained upon logic designing or mounting designing are substituted into the mathematical expressions to automatically check whether or not a total wiring line length, a branch length, a parallel wiring line length and a maximum load number are set so that generation of various kinds of noise may be suppressed.
Also measures for individually solving problems caused by various kinds of noise when designing is performed actually and such problems caused by various kinds of noise occur have been presented conventionally, and it is known that such measures are used to analyze crosstalk noise and reflection noise individually and perform a margin check, a delay/racing analysis and so forth of each kind of noise.
However, where such wiring rules on the document base or a wiring rule check tool on the mathematical expression base as described above is used, if the operating speed of a design object circuit is low, then it is possible to observe the wiring rules. However, as the operating speed is raised, it becomes difficult to design wiring lines so that the wiring rules (mathematical expressions) may be satisfied indiscriminately. Since the wiring rules are set taking various situations in which various kinds of noise are generated compositely into consideration so that generation of the various kinds of noise may be suppressed with certainty if the rules are observed, they are set very severely. Therefore, conventionally used wiring rules are excessive rules if the operating speed is raised, and cannot be used practically because a wiring line cannot be designed so as to satisfy the rules. When a wiring line cannot be designed so as to satisfy the rules in this manner, the designer designs ignoring the rules and takes a countermeasure against noise when a problem of noise occurs actually.
On the other hand, also measures for individually solving problems caused by noise have conventionally been presented as described above, such a technique as to perform a check of noise with generation timings of noise or delays in a net taken into consideration to systematically analyze various kinds of noise to actually produce an electronic circuit is not available. Accordingly, it cannot conventionally be avoided to check problems and so forth arising from noise by means of manual operations of a designer and a test of a circuit of a design object after the circuit is produced actually. Consequently, much time is required for the noise check and very high burden is imposed on the designer who analyzes the noise.
Further, there conventionally is a tendency that the influence of noise is evaluated unreasonably since noise is not analyzed with generation timings of noise and delays in a net taken into consideration. However, apparatus are complicated in function and augmented in speed in recent years as described above, and this results in severer design conditions for a circuit. Thus, it is demanded to systematically analyze different kinds of noise taking generation timings of noise and delays in a net into consideration and perform a margin check, a delay/racing analysis and so forth of noise based on a waveform proximate to an actual waveform.
Furthermore, an apparatus development cycle has been shortened in recent years. For example, in a personal computer, the development cycle is becoming shorter from a unit of a year to a unit of a month, and also it is demanded to shorten the time required for a noise check incidentally.
The present invention has been made in view of such a situation as described above, and it is an object of the present invention to provide a noise checking method and apparatus which makes it possible to systematically check/analyze various kinds of noise based on a signal waveform proximate to an actual signal waveform formed with the various kinds of noise taken into consideration to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check and besides realizes significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis.